`timescale 1ps / 1ps

module mem_write_A
#(
    parameter integer N1           = 4,
    parameter integer MATRIXSIZE_W = 16,
    parameter integer ADDR_W       = 12
)
(
    input  logic                    clk,
    input  logic                    rst,
    input  logic [MATRIXSIZE_W-1:0] M2,
    input  logic [MATRIXSIZE_W-1:0] M1dN1,
    input  logic                    valid_A,
    output logic  [ADDR_W-1:0]       wr_addr_A,
    output logic  [N1-1:0]           activate_A
);

logic [MATRIXSIZE_W-1:0] row_div;
logic [MATRIXSIZE_W-1:0] row_mod;
logic [MATRIXSIZE_W-1:0] col;

always_ff @(posedge clk) begin
    if(rst) begin
        wr_addr_A <= 0;
        activate_A <= 0;
        row_div <= 0;
        row_mod <= 0;
        col <= 0;
    end else begin
        if(valid_A) begin
            if(col < M2-1) begin
                col <= col + 1;
            end else begin
                col <= 0;
                if (row_mod == N1 - 1) begin
                    row_mod <= 0;
                    row_div <= row_div + M2;
                end else begin
                    row_mod <= row_mod + 1;
                end
            end

            wr_addr_A <= row_div + col;
            activate_A <= 1 << row_mod;
        end else begin
            wr_addr_A <= 0;
            activate_A <= 0;
        end
    end
end

endmodule